1. Field of the Invention
This invention relates to static random-access memories (SRAM), and more particularly to a SRAM cell and array layout.
2. Description of the Related Art
Static RAM memories are widely used as cache memories for central processing units (CPU's). Recently, cache RAM's have also been embedded on the processor die for microprocessor chips. Many have attempted and succeeded at reducing the size of the SRAM cell, and thus reducing the cost and speed delay of the memory.
FIG. 1 depicts a SRAM cell layout that is widely used. The physical layout of the six transistors in this cell 20 are shown as a stick diagram. The cell 20 contains a pair of cross-coupled inverters, each with a p-channel and an n-channel MOS transistor. These transistors are formed where polysilicon, shown as thick lines, cross active areas which are represented as rectangles or polygons. For example, one inverter comprises transistors TP.sub.1 and TN.sub.1, with transistor TP.sub.1 formed when polysilicon line N.sub.1 crosses over the p-channel active area containing contact 26 to Vdd, and transistor TN.sub.1 formed when polysilicon line N.sub.1 crosses over the n-channel active area containing contact 28 to ground. "X"es represents contacts between layers such as polysilicon, metal, or active silicon. The second inverter comprises transistors TP.sub.2 and TN.sub.2, with transistor TP.sub.2 formed when polysilicon line N.sub.2 crosses over the p-channel active area containing contact 26' to Vdd, and transistor TN.sub.2 formed when polysilicon line N.sub.2 crosses over the n-channel active area containing contact 28' to ground.
Two pass or access n-channel transistors TA.sub.1 and TA.sub.2 are provided to connect the cross-coupled inverters in cell 20 to a pair of bit lines BL, BLB. When these access transistors TA.sub.1, TA.sub.2 conduct, the cell may be read or written to using bit lines BL, BLB. Transistors TA.sub.1 and TA.sub.2 are formed when a polysilicon row or word line 30 crosses over the n-channel active areas, which are shared with the n-channel transistors TN.sub.1 and TN.sub.2. Polysilicon word line 30 may be `strapped` every 8-64 cells in metal to reduce the resistance. Bit-line contacts 22, 24 connect to bit lines BL, BLB, which run in metal over cell 20 in a vertical direction as shown.
Prior-art cell 20 has bit lines running in a vertical or y-axis direction, while row lines run in a horizontal or x-axis direction. For a three-layer metal process, the first layer of metal is used for interconnect within the cell, for cross-coupling the two inverters, as shown by the dashed thick lines of FIG. 1. The bit lines run in second metal, while the polysilicon word lines are strapped with third-layer metal. It is common to reverse the roles of the second and third layer metals.